Intersil ISL6323A Datasheet

This is a Monolithic Dual PWM Hybrid Controller that supports AMD SVI Split-Plane and PVI Uniplane processors and provides high efficiency and tight regulation of synchronous buck DC/DC converters.


Intersil ISL6323A Datasheet - cover page
Brand
Intersil
Category
Power Management
Document type
Datasheet
Language
English
Pages
35
File format
PDF
File size
834 KB
Published
28 March, 2012
Updated
30 September, 2023
Model
ISL6323
MD5 checksum
D3736AEB1836A66B320A12D6C62CFD7F

About this manual

The ISL6323A dual PWM controller provides high‑efficiency, tight regulation for two synchronous buck converters, supporting both serial (SVI) and parallel (PVI) VID interfaces used by AMD processors. It integrates MOSFET drivers, offers load‑line programming, and can shed phases for light‑load efficiency.

Key features include multi‑phase core voltage regulation, differential remote voltage sensing, adaptive phase alignment, over‑current and over‑voltage protection, selectable switching frequency up to 1 MHz, and a 5 V‑12 V variable gate‑drive bias.

What's inside

  • Features
  • Absolute Maximum Ratings
  • Electrical Specifications
  • Pinout
  • Controller Block Diagram
  • Typical Application - SVI Mode
  • Typical Application - PVI Mode
  • Package Outline Drawing

Specifications

Selectable Switching Frequencyup to 1 MHz
Variable Gate Drive Bias5 V to 12 V
Package type48‑lead QFN (L48.7×7 mm)

Frequently asked questions

What is the maximum switching frequency of the ISL6323A?

The device supports a selectable switching frequency up to 1 MHz.

What package does the ISL6323A use?

It is supplied in a 48‑lead quad flat no‑lead (QFN) package, 48.7 mm × 7 mm.

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