This manual provides information on the hardware characteristics and usage of the ADSP-TS101 TigerSHARC processor.
This 410‑page hardware reference for the ADSP-TS101 TigerSHARC processor provides in‑depth information on the DSP architecture, compute blocks, ALU, multiplier, shifter, and program sequencer. It includes detailed descriptions of core controls, interrupt handling, clock domains, and low‑power modes.
The manual also covers the full memory and register map, external bus and host interface specifications, SDRAM interface, DMA controller, and test/debug support. It serves engineers developing software and hardware for the ADSP-TS101 device.
| Word Page Size (1k) | 64‑bit bus width |
|---|---|
| Word Page Size (256) | 32‑bit bus width |
| Word Page Size (256) | 64‑bit bus width |
| Word Page Size (512) | 32‑bit bus width |
| Word Page Size (512) | 64‑bit bus width |
The processor supports 1 k, 256 byte, and 512 byte page sizes.
Each page size can be configured for either 32‑bit or 64‑bit bus width, depending on the setting.
The register map is detailed in the sections titled "Register Access Features" and "Register Space" within the manual.