The DS80C310 is a high-performance 80C31/80C32 compatible microcontroller. It features a redesigned processor core that eliminates wasted clock and memory cycles. As a result, it executes every 8051 instruction between 1.5x and 3x faster than the original architecture for the same crystal speed. Typical applications have a speed improvement of 2.5x using the same code and the same crystal. The DS80C310 offers a 25MHz maximum crystal speed, resulting in apparent execution speeds of 62.5MHz (approximately 2.5x). The DS80C310 is pin compatible with the standard 80C32 and includes standard resources such as three timer/counters, 256 bytes of RAM, and a serial port. It also provides dual data pointers (DPTRs) to speed block data memory moves. It also can adjust the speed of MOVX data memory access between two and nine machine cycles for flexibility in selecting external memory and peripherals. The DS80C310 offers upward compatibility with the DS80C320.
The DS80C310 is a fast 80C31/80C32‑compatible microcontroller featuring a redesigned core that executes 8051 instructions 1.5×‑3× faster than the original architecture. It supports a maximum crystal speed of 25 MHz, providing an apparent execution speed of about 62.5 MHz, and is pin‑compatible with the standard 80C32.
The device includes 256 bytes of on‑chip RAM, 64 kB of ROM, three 16‑bit timer/counters, a full‑duplex serial port, dual data pointers, and up to 10 interrupt sources. It is offered in 40‑pin DIP, 44‑pin PLCC, and 44‑pin TQFP packages, with temperature ranges from –40 °C to +85 °C depending on the part number.
| Maximum crystal speed | 25 MHz |
|---|---|
| On‑chip RAM | 256 bytes |
| On‑chip ROM | 64 kB |
| Timer/Counters | Three 16‑bit |
| Serial port | Full‑duplex |
| Interrupt sources | 10 |
The DS80C310 supports up to a 25 MHz crystal, giving an apparent execution speed of about 62.5 MHz.
The microcontroller provides ten interrupt sources with two priority levels.
Setting bit 1 of the Power Control Register (PCON; 87h) invokes the stop mode, the lowest power state.