High performance digital signal controllers
The dsPIC30F6011A/6012A/6013A/6014A family are high‑performance digital signal controllers with an improved RISC CPU, Harvard architecture, up to 30 MIPS operation and a 24‑bit instruction set. They include DSP capabilities such as dual 40‑bit accumulators, single‑cycle multiply‑accumulate, and a rich set of addressing modes.
These devices offer up to 144 KB of flash program memory, 8 KB of data RAM, 4 KB of EEPROM, 12‑bit ADC with 200 kS/s conversion rate, two CAN modules, two UARTs with FIFO, and multiple 16‑bit timers that can be paired for 32‑bit operation. They operate from 2.5 V to 5.5 V and support industrial temperature ranges. This manual is written in Chinese.
| Maximum CPU speed | 30 MIPS |
|---|---|
| Flash program memory | 144 KB |
| Data RAM | 8 KB |
| EEPROM | 4 KB |
| Operating voltage range | 2.5 V – 5.5 V |
| Interrupt sources | Up to 41 |
| CAN modules | 2 (CAN 2.0B compatible) |
The device can run at up to 30 MIPS.
They provide up to 144 KB of on‑chip flash program memory.
The controllers operate from 2.5 V to 5.5 V.
The device includes up to 41 interrupt sources.