This manual introduces the high-performance 16-bit digital signal controller dsPIC33FJXXXGPX06/X08/X10 and their features, and provides detailed hardware and software information.
The dsPIC33FJXXXGPX06/X08/X10 family is a high‑performance 16‑bit digital signal controller with an enhanced Harvard architecture, up to 40 MIPS CPU speed, and industrial‑grade temperature operation from –40 °C to +85 °C. It offers flexible clock options, on‑chip 2.5 V regulator, and multiple low‑power modes.
Key peripherals include up to 8‑channel DMA, up to 9 16‑bit timers (pairable as 32‑bit), SPI, I²C, UART, enhanced CAN, and up to two ADC modules with up to 32 input channels. The devices are offered in 64‑, 80‑ and 100‑pin TQFP packages with up to 256 KB flash and 30 KB SRAM (including 2 KB DMA RAM). This manual is written in Chinese.
| Maximum CPU performance | 40 MIPS |
|---|---|
| Operating voltage | 3.3 V ±10% |
| Temperature range | -40 °C to +85 °C |
| Flash program memory | 256 KB |
| SRAM (including DMA RAM) | 30 KB (2 KB DMA RAM) |
| Programmable digital I/O pins | 85 pins |
| DMA channels | 8 hardware channels |
| Timers | Up to 9 16‑bit timers (pairable as 4 32‑bit timers) |
The document is the Chinese version of the dsPIC33FJXXXGPX06/X08/X10 datasheet, with English parts included for reference.
Each device can contain up to 256 KB of flash program memory.
The controller includes an 8‑channel hardware DMA engine.