64Mb: x32 DDR SDRAM is a product of Micron Technology, Inc., which has bidirectional data storage buffer (DQS), internal pipelined double data rate (DDR) architecture, two data access cycles, reduced output drive option, differential clock inputs (CK and CK#), commands entered on each positive CK edge, DQS edge aligned with data for READs, center aligned with data for WRITEs, dynamic clock lock (DLL) to align DQ and DQS transitions with CK, four internal memory rows can work simultaneously, data mask (DM) for masking write data, programmable burst lengths: 2, 4, 8 or full page, 32 ms, 4096-cycle auto refresh (7.8µs/cycle), auto precharge option, auto refresh and self refresh modes, programmable input / output (SSTL_2 compatible) and other features