Analog Devices Manuals

This document describes the In-Circuit Flash Programming on ADSP-2106x SHARC® Processors. It is intended for system designers and engineers who need to update the system program in the field.

This document introduces the compatibility between Analog Devices' 28x28 MQFP and LQFP packages. It provides a land pattern design that accommodates both packages.

This manual describes programming information for SHARC® processors, including the ADSP-2136x, ADSP-2137x, and ADSP-214xx SHARC processors.

This document discusses the use of SHARC® EPROM and host boot loader

This document describes the external port DMA modes of operation supported on SHARC® processors, including DMA mode, trigger mode and read/write mode. All described modes are supported on ADSP-2106x and ADSP-2116x processors. The ADSP-21367, ADSP-21368, ADSP-21369 (hereafter referred to as ADSP-21368 processors), and ADSP-2137x processors external port supports master mode DMA operation only. These processors do not have the extra logic to support slave mode and read/write mode.

Describes In-Circuit Flash Programming on SHARC® Processors from Analog Devices, Inc.

Introduces the function and usage methods of VisualDSP++® Flash Programmer API

This document describes how to simultaneously run two network interfaces with ADSP-BF537 and ADSP-BF536 Blackfin® processors. It provides the hardware and software prerequisites and presents the test results based on a hardware setup consisting of an ADSP-BF537 EZ-Kit Lite® evaluation system and a Blackfin USB-LAN EZ-Extender card.

This EE-Note describes how to estimate, measure, and optimize the booting time of a Blackfin® processor-based system

This document describes how to use Analog Devices DSPs, processors, and development tools, as well as the transition times of Blackfin® processors between different operating modes.

PGO Linker is a code layout tool for Blackfin processors. It maps the most frequently executed code sections and critical real-time code to L1 SRAM memory to improve system performance.

This document describes the power-decoupling requirements for boards that contain SHARC® processors. It is intended to help system designers to calculate the total supply decoupling capacitance, choose the capacitor values, and place the capacitors for optimal results.

This file describes the characteristics and programming methods of the UART port controller of the SHARC processor

This EE-Note discusses the implementation of a delay line on the ADSP-2126x, ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 SHARC® series of processors.