Key facts
- Brand
- Lattice
- Model
- GAL20V8
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-05-09
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LATTICE SEMICONDUCTOR GAL20V8 High Performance E2 CMOS PLD Generic Array Logic handbook
The GAL20V8 is a high‑performance E²CMOS programmable logic device offering up to 166 MHz operation, 5 ns maximum propagation delay, and active pull‑ups on all pins. It supports reconfigurable logic, rapid electrical erasure (<100 ms), and up to 20‑year data retention, making it suitable for DMA control, state machines, and high‑speed graphics processing.
The document provides detailed specifications for commercial and industrial grade packages, pin‑out diagrams for DIP and PLCC formats, and explains the three global Output Logic Macrocell (OLMC) configuration modes—simple, complex, and registered—along with the associated architecture bits and usage restrictions.
Lattice GAL20V8 specifications
| Maximum propagation delay (Tpd) | 5 ns |
|---|---|
| Maximum clock‑to‑data output delay | 4 ns |
| Maximum operating frequency (Fmax) | 166 MHz |
| Typical Icc (Low Power device) | 75 mA |
| Typical Icc (Quarter Power device) | 45 mA |
| Erase/write cycles | 100 cycles |
| Data retention | ≥20 years |
| Registered mode clock pin | Pin 1 (CLK) |
| Registered mode output‑enable pin | Pin 13 (OE) |
Source: LATTICE SEMICONDUCTOR GAL20V8 High Performance E2 CMOS PLD Generic Array Logic handbook
All Lattice GAL20V8 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the maximum propagation delay of the GAL20V8?
The GAL20V8 has a maximum propagation delay of 5 ns.
From: LATTICE SEMICONDUCTOR GAL20V8 High Performance E2 CMOS PLD Generic Array Logic handbook
How many erase/write cycles are guaranteed for the GAL20V8?
The device is specified for 100 erase/write cycles.
From: LATTICE SEMICONDUCTOR GAL20V8 High Performance E2 CMOS PLD Generic Array Logic handbook
What are the three global OLMC configuration modes for the GAL20V8?
The GAL20V8 supports simple, complex, and registered OLMC configuration modes.
Which pins are permanently configured as clock and output‑enable in registered mode?
Pin 1 is permanently the clock (CLK) and Pin 13 is permanently the output‑enable (OE) in registered mode.