This application note explains the security architecture and features of the NXP LPC55S00 MCU for IoT devices.
The document introduces the LPC55S00 series, a family of Arm® Cortex‑M33 based MCUs designed for embedded and IoT applications. It outlines the overall security vision, lifecycle stages, and the need for built‑in protection throughout a device's life.
It then details the hardware security modules such as TrustZone‑M, hardware SRAM PUF, secure boot, PRINCE encryption, TRNG, DICE, SHA‑2, AES‑256 and protected flash (PFR). The note also covers secure boot, debug authentication, OTA firmware updates, and the process for establishing trusted communication with back‑end systems. This manual is written in Chinese.
| Flash Memory | up to 640 KB |
|---|---|
| RAM | up to 320 KB |
| ROM | 128 KB |
| Security Features | TrustZone‑M, SRAM PUF, Debug Authentication, PRINCE, TRNG, Secure Boot, DICE, SHA‑2, AES‑256, PFR |
The LPC55S00 includes TrustZone‑M, hardware SRAM PUF, debug authentication, real‑time PRINCE decryption, a true random number generator, secure boot, DICE, SHA‑2, AES‑256 encryption and protected flash (PFR).