NXP Semiconductors UM10204 I2C-bus specification and user manual introduces a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I2C-bus. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a uni-directional mode with data transfers of up to 5 Mbit/s.
This manual describes the I2C‑bus, a two‑wire serial communication standard developed by Philips Semiconductors (now NXP Semiconductors). It covers the bus architecture, signaling lines (SDA and SCL), and the various operating modes, including Standard, Fast, Fast‑mode Plus, High‑speed, and Ultra Fast‑mode.
The document includes timing diagrams, electrical characteristics, and design guidelines for system designers, IC designers, and manufacturers. It also explains multi‑master arbitration, clock stretching, and pull‑up resistor sizing, helping engineers implement reliable I2C‑bus solutions.
| Standard‑mode data rate | up to 100 kbit/s |
|---|---|
| Fast‑mode data rate | up to 400 kbit/s |
| Fast‑mode Plus data rate | up to 1 Mbit/s |
| High‑speed mode data rate | up to 3.4 Mbit/s |
| Ultra Fast‑mode data rate | up to 5 Mbit/s (unidirectional) |
| Bus lines | Two lines: SDA (serial data) and SCL (serial clock) |
The I2C‑bus uses two lines: a serial data line (SDA) and a serial clock line (SCL).
Ultra Fast‑mode supports unidirectional data transfers up to 5 Mbit/s.
Yes, the I2C‑bus is a multi‑master bus that includes arbitration to prevent data corruption when more than one master initiates a transfer.
The number of devices is limited by the total bus capacitance; higher capacitance may restrict the number of ICs.