This datasheet provides detailed information about the dsPIC30F2010 28-pin high-performance digital signal controller (DSC).
The dsPIC30F2010 is a 28‑pin, 16‑bit digital signal controller featuring an enhanced Harvard architecture, DSP engine, and motor‑control peripherals. It integrates 12 KB of flash program memory, 512 bytes of data RAM, and 1 KB of EEPROM, operating over a 2.5 V to 5.5 V supply range.
The document details the CPU core, memory organization, interrupt system, and peripheral modules such as PWM, QEI, SPI, I²C, UART, and a 10‑bit ADC capable of 500 Ksps. Electrical characteristics, package options, and development support resources are also included. This manual is written in Chinese.
| Flash program memory | 12 KB |
|---|---|
| Data RAM | 512 bytes |
| EEPROM | 1 KB |
| Working register array | 16 × 16 bits |
| Maximum instruction speed | 30 MIPS |
| Operating voltage range | 2.5 V – 5.5 V |
| ADC resolution and speed | 10‑bit, 500 Ksps |
| PWM output channels | 6 |
| Timer modules | 3 × 16‑bit timers/counters |
| SPI interfaces | 3‑wire SPI module |
| I²C addressing | 7‑bit/10‑bit |
The dsPIC30F2010 provides 12 KB of internal flash program memory.
It includes six PWM output channels that can be configured for complementary or independent operation.
The device operates from 2.5 V up to 5.5 V.
The controller can execute up to 30 MIPS.