The AD6641 is a 250 MHz bandwidth digital pre-distortion (DPD) observation receiver that integrates a 12-bit, 500 MSPS ADC. It offers high signal-to-noise ratio (SNR), effective number of bits (ENOB), and spurious-free dynamic range (SFDR). It also features excellent linearity and an integrated 16k × 12 FIFO. The AD6641 is suitable for applications such as wireless and wired broadband communications, communication test equipment, and power amplifier linearization.
The AD6641 is a 250 MHz bandwidth Digital Pre-Distortion (DPD) observation receiver designed for telecommunications applications. It integrates a 12-bit, 500 MSPS Analog-to-Digital Converter (ADC), a 16k × 12 FIFO, and a multi-mode backend. The device allows users to retrieve data stored in the integrated FIFO memory via Serial Port (SPORT), SPI, 12-bit parallel CMOS, or 6-bit DDR LVDS interfaces. It features excellent dynamic performance and low power consumption, making it suitable for wideband DPD observation paths. This manual is written in Chinese.
| Signal-to-Noise Ratio (SNR) | 65.8 dBFS |
|---|---|
| Effective Number of Bits (ENOB) | 10.5 bits |
| Spurious-Free Dynamic Range (SFDR) | 80 dBc |
| Differential Nonlinearity (DNL) | ±0.5 LSB |
| Integral Nonlinearity (INL) | ±0.6 LSB |
| Power Consumption | 695 mW |
| Analog Input Bandwidth | 1 GHz |
The maximum sampling rate is 500 MSPS.
Data can be retrieved via Serial Port (SPORT), SPI, 12-bit parallel CMOS, or 6-bit DDR LVDS interfaces.
The typical power consumption is 695 mW at 500 MSPS.