This is a user guide for Serial Digital Interface (SDI) MegaCore Function, which describes the features and functionalities of the product.
This document describes the Altera Serial Digital Interface (SDI) MegaCore Function and the accompanying SDI Audio IP cores. The SDI MegaCore function implements a receiver, transmitter, or full-duplex SDI at standard definition (SD), high definition (HD), or 3 gigabits per second (3G). It supports dual standard (HD-SDI and SD-SDI) and triple standard (SD-SDI, HD-SDI, and 3G-SDI) modes, providing automatic receiver rate detection.
The guide covers features such as cyclic redundancy check (CRC) encoding and decoding, line number insertion and extraction, word scrambling and descrambling, and framing of video timing signals. It details the design flow, including creating a new Quartus II project, launching the MegaWizard Plug-In Manager, setting up simulation, specifying constraints, and programming a device. The document also includes functional descriptions of the transmitter and receiver blocks, parameters, and verification information.
| Supported Standards | SD, HD, 3G |
|---|---|
| Simulation Support | VHDL and Verilog HDL simulators |
It supports standard definition (SD), high definition (HD), and 3 gigabits per second (3G).
Yes, the dual and triple standard modes provide automatic receiver rate detection.