Altera FIFO Partitioner Megafunction User Guide

About this manual

The FIFO Partitioner is a tool designed to map multiple First-In-First-Out (FIFO) buffers into a single physical Stratix M-RAM block. It automatically generates the necessary logic to time-domain-multiplex the memory block between multiple user-specified FIFOs, enhancing the utility of the TriMatrix memory architecture. This feature is particularly useful for FIFO functions that cannot be efficiently fit into standard M512 or M4K blocks.

What's inside

• Introduction
• Features
• Specifying a FIFO Partitioner Function Using the FIFO Partitioner MegaWizard
• Specifying Global Configuration Options
• Specifying FIFO Configurations
• Frequency Information
• FIFO Functionality
• Synthesizing FIFO Partitioner Functions
• Static Timing Analysis for FIFO Partitioner Functions
• Simulating FIFO Partitioner Functions

Specifications

Frequently asked questions

What is the FIFO Partitioner?

The FIFO Partitioner is a tool for mapping multiple FIFOs into a single physical memory block.

How does the FIFO Partitioner operate?

It automatically generates the logic necessary to time-domain-multiplex Stratix M-RAM blocks between multiple user-specified FIFOs.

Can FIFO ports operate in asynchronous clock domains?

Yes, FIFO ports can be operated in completely asynchronous clock domains.