This guide describes the Altera Nios II processor custom instructions, including instruction formats, instruction encoding, data types, operands, registers and memory accesses, and the use and writing of custom instructions. The guide also discusses optimization of custom instructions and the limitations imposed by memory management and instruction scheduling.
The Nios II Custom Instruction User Guide describes how system designers can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. These custom instructions allow complex sequences of standard instructions to be reduced to a single instruction implemented in hardware, optimizing software inner loops for applications such as digital signal processing and packet header processing.
The document details the hardware block diagrams, different types of custom instructions (combinational, multi-cycle, extended, internal register file, and external interface), and the software interface. It provides step-by-step instructions for implementing custom instruction hardware using SOPC Builder and accessing them from software via C/C++ macros or assembly language.
| Maximum number of custom instructions | 256 |
|---|---|
| Processor core version | 8.0 |
| Document version | 1.5 |
They allow system designers to accelerate time-critical software algorithms by converting complex sequences of standard instructions into a single hardware instruction.
They are implemented as custom logic blocks adjacent to the processor's arithmetic logic unit (ALU) in the data path.
Developers can use C or C++ application code where the IDE generates a macro in the system header file, or they can use Nios II processor assembly language.