This manual introduces the features and usage of the Altera Phase-Locked Loop (ALTPLL) Megafunction. ALTPLL is an important clock generation module in Altera FPGA devices. It can be used to generate stable frequencies, recover signals from a noisy communication channel, or distribute clock signals throughout your design.
The Phase-Locked Loop (PLL) is a closed-loop frequency-control system used to generate stable frequencies, recover signals, and distribute clock signals. The ALTPLL megafunction provides a configurable interface within Quartus II software to implement these circuits in supported Altera device families, including Stratix, Cyclone, Arria, and Hardcopy series.
The pre-divider counter divides the input clock frequency to create the reference frequency.
The output frequency is calculated by multiplying the input clock by M and dividing by the product of N and K.
There are 12 PLLs available for configuration in the Stratix IV device family.