This user guide describes the parallel flash loader (PFL) megafunction and provides information about programming flash memory, configuring your FPGA from the flash memory, and instantiating the PFL megafunction in the Quartus® II software. As the density of FPGAs increases, larger configurations need to be configured on the FPGA, and faster configuration speeds are required. The PFL addresses these issues.
This user guide describes the Parallel Flash Loader (PFL) megafunction, which allows users to program flash memory devices and control FPGA configuration from flash memory. The PFL megafunction supports programming Common Flash Interface (CFI), quad Serial Peripheral Interface (SPI), and NAND flash memory devices via the JTAG interface. It enables efficient programming of flash memory devices through Altera CPLDs and FPGAs.
| Supported Flash Types | CFI flash, quad SPI flash, or NAND flash memory devices |
|---|---|
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria series, Cyclone series, FLEX 10K, and Stratix series |
| Supported File Formats | Programmer Object File (.pof), Jam Standard Test and Programming Language Format File (.jam), or JAM Byte Code File (.jbc) |
The PFL megafunction supports programming Common Flash Interface (CFI) flash, quad Serial Peripheral Interface (SPI) flash, or NAND flash memory devices.
Yes, it controls Altera FPGA configuration from a CFI flash, quad SPI flash, or NAND flash memory device.