This document describes the features and characteristics of the Altera FIR Compiler
The Altera FIR Compiler provides a fully integrated development environment for finite impulse response (FIR) filters optimized for Altera FPGA devices. It supports various hardware architectures, including fully parallel, serial, and multibit serial distributed arithmetic, as well as multicycle variable structures. The tool automatically generates code for Quartus II software and includes a coefficient generator for efficient design space exploration.
Key features include precision control of chip resource utilization, support for run-time coefficient reloading, and user-selectable output precision. The guide covers installation, parameter settings, functional descriptions, and implementation details for different filter structures.
| Version | 11.0 |
|---|---|
| Release Date | May 2011 |
| Ordering Code | IP-FIR |
| Product ID | 0012 |
| Vendor ID | 6AF7 |
The FIR Compiler supports fully parallel, fully serial, multibit serial distributed arithmetic, and multicycle variable structures.
Yes, it includes a built-in coefficient generator to enable efficient design space exploration.
Yes, the FIR Compiler is DSP Builder ready.