This is a user guide for the FIR Compiler II MegaCore function, which describes the features and characteristics of the product.
The Altera FIR Compiler II MegaCore function provides a fully integrated finite impulse response (FIR) filter optimized for use with Altera FPGA devices. It includes an interactive parameter editor that allows users to easily create custom FIR filters and outputs IP functional simulation model files for use with Verilog HDL and VHDL simulators.
The core supports various filter types, including single rate, decimation, interpolation, and fractional rate filters. Key features include hardware optimizations such as symmetry and time sharing, easy system integration using Avalon Streaming interfaces, and support for run-time coefficient reloading and multiple coefficient banks.
| Supported Device Families | Arria, Cyclone, HardCopy, Stratix |
|---|---|
| Filter Types Supported | single rate, decimation, interpolation, and fractional rate filters |
| Interface Type | Avalon Streaming (Avalon-ST) |
| Simulation Tools | Verilog HDL and VHDL simulators |
Yes, it supports run-time coefficient reloading capability and multiple coefficient banks.
The parameter editor outputs simulation model files for use with Verilog HDL and VHDL simulators.