This user guide provides information on how to use Altera's DDR and DDR2 SDRAM Controller Compiler (DDR SDRAM Controller Compiler) and provides usage guidelines.
The document provides a user guide for the Altera DDR and DDR2 SDRAM Controller Compiler, specifically version 9.0 released in March 2009. It covers the MegaCore functions for DDR and DDR2 SDRAM devices, detailing how they simplify interfaces to industry-standard memory devices by handling initialization, bank management, and refresh intervals.
| Version | 9.0 |
|---|---|
| Release Date | March 2009 |
| Vendor ID | 6AF7 |
| Product ID (DDR SDRAM) | 0055 |
| Product ID (DDR2 SDRAM) | 00A7 |
The compiler supports Cyclone II, HardCopy III, Stratix II, Stratix GX, and Stratix II GX devices, with varying levels of support for DDR and DDR2.
The ordering codes are IP-SDRAM/DDR for DDR SDRAM and IP-SDRAM/DDR2 for DDR2 SDRAM.