This article introduces an innovative verilog model for predicting the DC, small signal, and large signal behavior of LDMOS. The model is simple and provides a good approximation of the DC, small signal S-parameter, and large signal behavior. It can serve as a starting point for designers in developing new applications.
The document introduces a behavioral Verilog-A model designed to simulate RF LDMOS power transistor characteristics. The model includes parasitic elements associated with the package and a thermal node to account for self-heating effects, implemented within Agilent Advanced Design System (ADS).
The note details the parameter extraction process specifically for the PD54003L-E device, a 3 W LDMOS housed in a PowerFLAT plastic package. It covers equations for nonlinear current generators, JFET resistance, and substrate-body diodes, validated using the DB-54003L-175 demoboard over the 135-175 MHz frequency band.
| Device Power Rating | 3 W |
|---|---|
| Operating Voltage | 7.2 V |
| Frequency Range | 500 MHz |
| Package Type | PowerFLAT plastic package (5 x 5 mm) |
| Operating Frequency Band | 135-175 MHz |
The model has been implemented in Agilent Advanced Design System.
Yes, it includes a thermal node which takes self heating effects into account.
To help RF Engineers predict and simulate the behavior of RF power transistors to reduce design cycle time.