AN1019 Application Note: Dual Footprint for SNAPHAT Devices

By integrating a battery and power switching circuitry in its ZEROPOWER memory devices, STMicroelectronics was the first to develop non-volatile CMOS Static RAM technology. This is conventional, high speed, low power, random access, read/write memory that retains its data even when the external power is removed. By further integrating a crystal oscillator and a real time clock in the package for its TIMEKEEPER products, STMicroelectronics provides, in a single chip package, non-volatile SRAM and timekeeping that continues to run without external power. STMicroelectronics has subsequently extended the technique to work with surface mount packaging, in a product range that is known as the SNAPHAT.


AN1019 Application Note: Dual Footprint for SNAPHAT Devices - cover page
Brand
STMicroelectronics
Category
Memory
Document type
Application Note
Language
English
Pages
3
File format
PDF
File size
40 KB
Published
06 August, 2012
Updated
28 September, 2023
MD5 checksum
08ED55967EEEC6E75C70B032D59C0729

About this manual

STMicroelectronics developed non-volatile CMOS Static RAM technology integrating battery and power switching circuitry in its ZEROPOWER memory devices. This technology was extended to surface mount packaging known as SNAPHAT, which allows the battery and crystal to be mounted on top of the SOIC package after the surface-mount process is completed.

The document provides a recommended dual footprint design for customers seeking an alternative source for STMicroelectronics M48T58, M48T59, or M48T35 devices. This suggested board layout utilizes a Dallas Semiconductor hybrid surface mount device to provide compatibility.

What's inside

  • SNAPHAT Technology
  • Dual Footprint Design
  • Dallas Semiconductor Hybrid Device
  • M48T58 Alternative
  • Board Layout Guidelines

Frequently asked questions

What alternative device can be used for the M48T58, M48T59, or M48T35?

A Dallas Semiconductor hybrid surface mount device can be used as an alternative.

What is the minimum width and space for the traces in the suggested board layout?

The traces have a minimum width and space of 6 mils.

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