High performance 32-bit/40-bit floating point processor optimized for high performance audio processing
The document describes the ADSP-21371 and ADSP-21375, members of the SIMD SHARC family featuring Analog Devices' Super Harvard Architecture. These processors are 32-bit/40-bit floating-point devices optimized for high-performance automotive audio applications, utilizing large on-chip SRAM and mask-programmable ROM to eliminate I/O bottlenecks.
| Instruction Cycle Time (266 MHz) | 3.75 ns |
|---|---|
| Maximum Performance (266 MHz) | 1.596 GFLOPS |
| On-Chip SRAM (ADSP-21371) | 1M bits |
| On-Chip ROM (ADSP-21371) | 4M bits |
| On-Chip SRAM (ADSP-21375) | 0.5M bits |
| On-Chip ROM (ADSP-21375) | 2M bits |
| Serial Ports (ADSP-21371) | 8 |
The ADSP-21371/ADSP-21375 processors are available with a 200 or 266 MHz core instruction rate.
Yes, they are code compatible with all other members of the SHARC family and previous ADSP-2106x, 2116x, 2126x, and 2136x DSPs.
The ADSP-21371/ADSP-21375 are available in a 208-lead LQFP_EP package.