This document is the hardware reference manual for the ADSP-BF537 Blackfin® processor, including the ADSP-BF534 and ADSP-BF536 Blackfin processors. The document describes the features and characteristics of the products.
The document serves as a comprehensive hardware reference for the ADSP-BF537 Blackfin processor. It includes detailed information on the processor's internal memory architecture, peripheral subsystems such as DMA, Ethernet MAC, and various serial interfaces (UART, SPI, I2C), and system interrupt controllers.
The manual covers the chip bus hierarchy, including the Core Bus, Peripheral Access Bus (PAB), and External Access Bus (EAB). It provides extensive descriptions of register definitions, timing specifications for external memory interfaces like SDRAM, and operational modes for power management.
This document covers the ADSP-BF537 Blackfin Processor and also includes information for the ADSP-BF534 and ADSP-BF536 Blackfin Processors.
When the CL bits in the SDRAM memory global control register are set to 00, that specific value is reserved.