SI S41C6105 S41LV16105 handbook

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SI S41C6105 S41LV16105 handbook - cover page
Brand
SI
Category
Memory
Document type
Datasheet
Language
English
Pages
18
File format
PDF
File size
519 KB
Published
02 August, 2012
Updated
30 September, 2023
MD5 checksum
4B26D113CF8308C008C7E0B8136E413E

About this manual

The IS41C16105 and IS41LV16105 are 1.048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices feature fast page mode, allowing 1.024 random accesses within a single row with access cycle times as short as 20 ns per 16-bit word. They are available in 5V and 3.3V versions and are packaged in 42-pin SOJ and 44-pin TSOP-2 formats.

What's inside

  • Features
  • Key Timing Parameters
  • Description
  • Pin Configurations
  • Functional Block Diagram
  • Truth Table
  • Functional Description
  • Memory Cycle
  • Refresh Cycle
  • Electrical Characteristics

Specifications

Memory Size1M x 16 (16-MBIT)
Refresh Interval1.024 cycles/16 ms
Operating Temperature (Industrial)-40 to +85 C
Max. RAS Access Time (tRAC)50 ns
Min. Fast Page Mode Cycle Time (tc)20 ns
Supply Voltage5V or 3.3V

Frequently asked questions

What is the memory capacity of the IS41LV16105?

The device is a 1.048,576 x 16-bit high-performance CMOS Dynamic Random Access Memory.

Does the IS41LV16105 support fast page mode?

Yes, it supports fast page mode which allows 1.024 random accesses within a single row.

What are the available package types for this DRAM?

The devices are packaged in a 42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2.

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