This is a technical manual that introduces the MPC7441, including function characteristics, electrical characteristics, packaging dimensions, etc.
This document provides hardware specifications for the Motorola MPC7441EC/D, a reduced instruction set computing (RISC) microprocessor implementing the PowerPC 32-bit architecture. It is targeted at networking and computing systems applications.
The datasheet covers electrical and physical characteristics of the processor, including features such as superscalar execution, branch prediction, and cache hierarchies. For functional characteristics, users are directed to refer to the MPC7450 RISC Microprocessor Family User's Manual.
| Architecture | PowerPC 32-bit architecture |
|---|---|
| L2 Cache Size | 256-Kbyte |
| Instruction Fetch Width | 4 instructions per cycle |
| Issue Queue Depth | 12 entries |
| Simultaneous Execution | 16 instructions |
| Pipeline Stages | Seven-stage pipeline control |
| Integer Units | Four integer units (IUs) |
| FPU Compliance | IEEE 754-1985-compliant |
| Vector Units | Four vector units |
| L1 Cache Size | 32-Kbyte |
The MPC7441 implements the full PowerPC 32-bit architecture.
Refer to the MPC7450 RISC Microprocessor Family User's Manual for functional characteristics.
Yes, the document is preliminary and subject to change without notice.