AMD SR5650 Technical Reference Manual
The document serves as a comprehensive technical reference manual for the AMD SR5650 chipset. It details the device's architecture, including support for multiple processors and Northbridges via HyperTransport interfaces, as well as PCI Express connectivity.
Key sections cover functional descriptions of interrupt handling, reliability features like parity protection, and detailed pin assignments with strap options. The manual also includes specific timing specifications for bus operations, electrical characteristics such as maximum ratings and DC parameters, thermal data, and power management implementation guidelines.
The part number for this document is 47062_sr5650_ds_pub.
This manual is Revision 2.10.
The latest revision, 2.10, was released in June 2011.