CD54AC112 and CD74AC112 are dual J-K negative-edge-triggered flip-flops with clear and preset. The device contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
This document is a technical datasheet for the CD54AC112 and CD74AC112 devices, which contain two independent J-K negative-edge-triggered flip-flops. These components feature balanced noise immunity at 30% of the supply voltage and significantly reduced power consumption compared to bipolar F, AS, and S types.
| Supply Voltage Range | 1.5 V to 5.5 V |
|---|---|
| Output Drive Current | +24-mA Output Drive Current |
| Fanout Capacity | 15 TTL Devices |
| Operating Temperature Range (Industrial) | -55°C to 125°C |
They are dual J-K negative-edge-triggered flip-flops with clear and preset.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of other inputs.