The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.
The document is a product specification sheet for the 74HC/HCT573 integrated circuit. It describes the device as high-speed Si-gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL). The chip features eight D-type transparent latches with separate inputs and common 3-state output enable and latch enable inputs, making it suitable for bus-oriented applications.
| TTL Compatibility | Compatible with LSTTL |
|---|---|
| Number of Latches | Octal (8) |
| Output Type | 3-state non-inverting |
| Propagation Delay (HC) | 14 ns typical |
The contents of the 8 latches are available at the outputs.
When the OE input is LOW, the contents of the latches are available at the outputs, and when it is HIGH, the outputs go to the high impedance OFF-state.
The set-up time for the D input to LE transition is 13 ns to 20 ns for the 74HCT series.