74HC/HCT7731 is a high-speed, single-pole, static shift register with recycling mode. Each register has independent data input pins Da to Dd, clock input pins CPa to CPd, and data output pins Qa to Qd. When the clock pulse changes from low to high, the data is shifted one place to the output end. Each recycling mode input controls two registers, RECab controls registers A and B, and RECcd controls registers C and D. When the REC input is high, the device is in the recycling mode and the data at the output end is shifted back to the input end of the register. This makes the data continuously repeated 64 times.
The document describes the HC/HCT7731 as high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no. 7A. These are quad 64-bit static shift registers that include a recycling mode, allowing data to be shifted back into the input after 64 clock pulses.
| Frequency range | DC to 100 MHz |
|---|---|
| Device type | Quad 64-bit static shift register |
| Technology | Si-gate CMOS |
| Standard compliance | JEDEC standard no. 7A |
| Output capability | Standard |
The document lists data storage and delay line applications for the 74HC/HCT7731.
After 64 clock pulses, the contents of a register return to their original position.
The maximum clock frequency for the HC version is 100 MHz.