This document describes the features and characteristics of the 74HC/HCT4020 14-stage binary ripple counter. It has standard output capability and is suitable for MSI category. The counter has a clock input, an overriding asynchronous master reset input, and twelve fully buffered parallel outputs. The counter advances on the HIGH-to-LOW transition of the clock input. When the master reset input is HIGH, all counter stages are cleared and all outputs are forced LOW, regardless of the state of the clock input. Each counter stage is a static toggle flip-flop.
