This document describes the features and characteristics of the 74HC/HCT4020 14-stage binary ripple counter. It has standard output capability and is suitable for MSI category. The counter has a clock input, an overriding asynchronous master reset input, and twelve fully buffered parallel outputs. The counter advances on the HIGH-to-LOW transition of the clock input. When the master reset input is HIGH, all counter stages are cleared and all outputs are forced LOW, regardless of the state of the clock input. Each counter stage is a static toggle flip-flop.
This datasheet describes the 74HC/HCT4020, a high-speed Si-gate CMOS integrated circuit functioning as a 14-stage binary ripple counter. The device is pin compatible with the '4020' of the '4000B' series and features a clock input (CP), an overriding asynchronous master reset input (MR), and twelve fully buffered parallel outputs.
| Number of stages | 14-stage binary ripple counter |
|---|---|
| Clock input transition | HIGH-to-LOW |
| Maximum clock frequency (HC) | 52 MHz |
| Maximum clock frequency (HCT) | 47 MHz |
The device is a 14-stage binary ripple counter.
The counter advances on the HIGH-to-LOW transition of the CP input.
A HIGH signal on MR clears all stages and forces every output LOW, regardless of the clock state.