74HC/HCT4017 are high-speed Si-gate CMOS devices and are pin compatible with the “4017” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4017 are 5-stage Johnson decade counters with 10 decoded active HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automat
The Philips 74HC/HCT4017 is a high-speed Si-gate CMOS device functioning as a 5-stage Johnson decade counter. It features 10 decoded active HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9), and active HIGH and active LOW clock inputs. The device includes an overriding asynchronous master reset input and provides automatic code correction, returning to a proper counting mode within 11 clock pulses following any illegal code.
The datasheet provides typical quick reference data, pin descriptions, logic diagrams, timing diagrams, and AC/DC characteristics for both HC and HCT variants. It also includes application information for decade counting, 1-out-of-n decoding, sequential controllers, and timers, along with techniques for counter expansion and pulse width enlargement.
| Maximum clock frequency | 77 MHz (HC) / 67 MHz (HCT) |
|---|---|
| Input capacitance | 3.5 pF |
| Power dissipation capacitance per package | 35 pF (HC) / 36 pF (HCT) |
| Supply voltage condition (HC) | GND to Vcc |
| Supply voltage condition (HCT) | GND to Vcc - 1.5 V |
An overriding asynchronous master reset input (MR) resets the counter to zero independent of the clock inputs.
Automatic code correction is provided by an internal circuit, returning the counter to a proper counting mode within 11 clock pulses.
Yes, the Q5-9 output, which is LOW while the counter is in states 5 through 9, can be used to drive the CP9 input of the next counter.