The CMT2301 is a P-channel logic enhancement mode power field effect transistor produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits, and low in-line power loss are needed in a very small outline surface mount package.
This document is a technical datasheet for the Champion CMT2301, a P-Channel logic enhancement mode power field effect transistor. The device utilizes high cell density DMOS trench technology to minimize on-state resistance.
The CMT2301 is designed for low voltage applications such as cellular phones and notebook computers. It features a SOT-23-3 package with a maximum drain-to-source voltage of -20V and continuous drain currents ranging from -1.5A to -2.5A depending on temperature.
| Drain-to-Source Voltage (Vdss) | -20 V |
|---|---|
| Package Type | SOT-23-3 |
| Operating Junction Temperature | -55/150 C |
The device is suited for power management in notebook portable equipment, battery powered systems, DC/DC converters, load switches, and LCD display inverters.
The drain-source on-resistance (Rds(on)) is a maximum of 0.13 Ohms when Ids = -2.8A.