ICS ICS9148-11 Frequency Generator and Integrated Buffers Datasheet

This document is a product specification manual, which mainly introduces the characteristics of the product, such as operating frequency and clock frequency.


ICS ICS9148-11 Frequency Generator and Integrated Buffers Datasheet - cover page
Brand
ICS
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
14
File format
PDF
File size
570 KB
Published
11 June, 2012
Updated
28 September, 2023
MD5 checksum
0BFFA54B2B3A3A3DF44ECB6A2A8DE14F

About this manual

The ICS9148-11 is a frequency generator and integrated buffer designed for high-speed RISC or CISC microprocessor systems, such as Intel PentiumPro. It generates four processor clocks, six bus clocks, one 14.318MHz clock, and twelve SDRAM clocks with synchronous skew matching.

The device features power management capabilities controlled by the MODE pin, allowing for CPU_STOP#, PCI_STOP#, and PWR_DWN# functions. It includes a serial configuration interface via I2C protocol and is available in a 48-pin SSOP package.

What's inside

  • General Description
  • Features
  • Pin Configuration
  • Functionality Table
  • Power-On Conditions
  • Technical Pin Function Descriptions
  • Power Groups

Frequently asked questions

What is the nominal voltage for the VDD(1:3) power supply?

The nominal voltage for the VDD(1:3) power supply is 3.3V.

What is the maximum latency for the Power Down function?

The latency of Power Down will not be greater than 3ms.

What is the minimum turn-on latency for the CPUCLKs when stopped?

The CPUCLKs will have a turn ON latency of at least 3 CPU clocks.

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