Motorola MC92501 ATM Cell Processor Technical Data Sheet

MC92501 is the second generation ATM cell processor in MotorolaÕs 92500 series. It provides comprehensive ATM layer functions, and is compliant with UTOPIA Level 2 physical and switch interfaces.


Motorola MC92501 ATM Cell Processor Technical Data Sheet - cover page
Brand
Motorola
Document type
Datasheet
Language
English
Pages
52
File format
PDF
File size
296 KB
Published
06 June, 2012
Updated
30 September, 2023
MD5 checksum
B79076C84CD7B182483EDAB85D37ED89

About this manual

The Motorola MC92501 is a second-generation Asynchronous Transfer Mode (ATM) layer device designed for use in ATM switches. It combines dedicated high-performance ingress and egress cell processors with UTOPIA Level 2-compliant physical (PHY) and switch interface ports to handle broadband ISDN applications according to ATM Forum, ITU, and Bellcore specifications.

This document outlines the new features of the MC92501 compared to its predecessor, including support for ABR Relative Rate Marking, selective discard capabilities, and enhanced microprocessor interfaces. It serves as a technical reference providing complete specifications when combined with the MC92500/D datasheet.

What's inside

  • ATM Network Description
  • Functional Description
  • Packet-Based UPC Discard Algorithms
  • Selective Discard
  • Available Bit Rate (ABR) Support
  • CLP Transparency
  • Indirect External Memory Access
  • Improved Host Interface
  • Register Descriptions
  • Electrical Characteristics

Frequently asked questions

What standards does the MC92501 implement for ATM layer functions?

It implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 Specifications, ITU Recommendations, and Bellcore Recommendations.

What is the maximum data rate supported by existing MC92500 features?

The device supports full-duplex operation at data rates up to 155 Mbit/sec.

How many physical links can the MC92501 support?

The device supports up to 16 Physical Links using dedicated ingress/egress MultiPHY control signals.

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