The document details the specifications for the 54LS173/DM74LS173A, a four-bit register containing D-type flip-flops with totem-pole TRI-STATE outputs. These outputs are designed to interface directly with system buses without requiring additional pull-up components.
Data is loaded on the next positive transition of the buffered clock when both data-enable inputs are low.
The maximum clock frequency is 30 MHz.
It can sink up to 24 mA of low-level output current.