This document describes the features and characteristics of the TMC2302A product, including asynchronous loading of control parameters, rapid rotation, warping, panning, and scaling of images, three-dimensional image addressing capability, general third-order polynomial transformations in two dimensions on-chip, support for up to order 1.5 three-dimensional transformations, flexible user-configurable pixel datapath timing structure, static convolutional filtering, selectable source image subpixel resolution, 24-bit (optional 36-bit) positioning precision, low power CMOS process, and available packaging options.
The TMC2302A is a versatile, high-performance integrated circuit designed as an asynchronous loading control parameter sequencer. It supports rapid image manipulations such as rotation, warping, panning, and scaling with speeds up to 40 MHz. The device utilizes general third-order polynomial transformations in two dimensions and can support three-dimensional transformations of up to order 1.5.
The device performs these image manipulations at a speed of 25ns per pixel.
Source image addresses may be generated at up to 40MHz.
A system based on two TMC2302As can complete this task in 6.5 milliseconds.