PSD4235G2 is a Philips chip-on-board that integrates configurable memories, PLD logic and I/O, and can be used in 16-bit MCU applications. It has 4 Mbit of main memory, 256 Kbit of auxiliary memory, 64 Kbit of SRAM, and 3000 gates of PLD.
The PSD4235G2 is a Flash In‑System Programmable (ISP) peripheral designed for 16‑bit microcontrollers. It integrates dual‑bank flash memories, battery‑backed SRAM, and programmable logic (CPLD/DPLD) with 52 configurable I/O pins.
The manual provides a summary description, programming options via JTAG (ISP) and MCU‑controlled IAP, architectural overview, memory and PLD details, VO port configuration, power‑management information, pin assignments, and electrical specifications.
| Primary Flash Memory | 4 Mbit (8 sectors, 32K x 16) |
|---|---|
| Secondary Flash Memory | 256 Kbit (4 sectors) |
| SRAM | 64 Kbit (battery backed) |
| I/O Pins | 52 individually configurable pins |
| PLD Gate Count | Over 3000 gates |
| CPLD Macrocell Count | 16 Output Macrocells, 24 Input Macrocells |
| Flash Endurance | 100,000 erase/write cycles |
| PLD Endurance | 1,000 erase/write cycles |
| Data Retention | 15 years |
| Memory Access Time | 70 ns |
It provides 52 individually configurable I/O pins.
The flash memory is rated for 100,000 erase/write cycles.