Texas Instruments DIT4096 Digital Audio Transmitter Datasheet

This document introduces the features and characteristics of the DIT4096 digital audio transmitter. The product complies with AES-3, IEC-60958 and EIAJ CP1201 interface standards, supports sampling rates up to 96kHz, supports mono mode operation, integrates differential line driver, has a flexible audio serial interface, supports I2S, left-aligned and right-aligned data formats, supports software mode and hardware mode, and supports CRC code generation.


Texas Instruments DIT4096 Digital Audio Transmitter Datasheet - cover page
Brand
Texas Instruments
Category
Audio Codec
Document type
Datasheet
Language
English
Pages
25
File format
PDF
File size
540 KB
Published
11 May, 2012
Updated
30 September, 2023
MD5 checksum
9D90B53396E8AE56C3CD802F85772B06

About this manual

The DIT4096 digital audio transmitter is designed for professional and consumer audio applications, supporting sampling rates up to 96 kHz and complying with AES‑3, IEC‑60958, and EIAJ CP1201 standards. It offers both software and hardware control modes, a flexible audio serial interface, and on‑chip differential line driver.

The device operates from a 5 V core supply (Vop) and a 2.7 V‑5 V logic supply (Vio), with a maximum master clock frequency of 25 MHz. It is supplied in a 28‑lead TSSOP package and includes ESD protection and detailed reset and power‑down procedures.

What's inside

  • Features
  • Applications
  • Absolute Maximum Ratings
  • Package/Ordering Information
  • Electrical Characteristics
  • Pin Configuration
  • General Description
  • Master Clock
  • Reset and Power‑Down Operation
  • Audio Serial Port

Specifications

Maximum sampling rate96 kHz
Package typeTSSOP‑28
Core supply voltage (Vop)4.5 V – 5.5 V
Logic supply voltage (Vio)2.7 V – 5 V
Maximum master clock frequency25 MHz
Power dissipation (dynamic, 96 kHz)150 mW

Frequently asked questions

What master clock frequency can be supplied to the DIT4096?

The device accepts a master clock up to 25 MHz on the MCLK pin.

Which audio data formats are supported?

It supports Left‑Justified, Right‑Justified, and I²S (Phillips) formats.

How is the reset sequence performed?

Assert the RST pin low for at least 500 ns, then release it high to start normal operation.

What is the package style of the DIT4096?

The part is supplied in a 28‑lead TSSOP package.

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