The ADC12DL066 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance and a 450 MHz Full Power Bandwidth. Operating on a single 3.3V power supply, the ADC12DL066 achieves 10.7 effective bits and consumes just 686 mW at 66 MSPS, including the reference current. The Power Down feature reduces power consumption to 75 mW. The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADCs are available on separate 12-bit buses with an output data format choice of offset binary or two's complement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL066 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C.
The ADC12DL066 is a dual, low‑power CMOS analog‑to‑digital converter that converts analog signals to 12‑bit digital words at a minimum of 66 MSPS. It operates from a single +3.3 V supply, offers an internal sample‑and‑hold, and provides differential inputs with a 450 MHz full‑power bandwidth.
The document includes detailed pin descriptions, absolute maximum ratings, DC/AC electrical characteristics, and application guidelines such as recommended layout, reference handling, and common pitfalls for high‑speed operation.