The M5M4V64S20ATP-8, -10, -12 is a 4-bank x 4194304-word x 4-bit Synchronous DRAM from Mitsubishi Electric with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
The M5M4V64S20ATP is a 64‑Mbit (4‑bank × 4 194 304‑word × 4‑bit) synchronous DRAM with an LVTTL interface, intended for use as main or graphics memory in computer systems. It operates with a single 3.3 V + 0.3 V power supply and supports three clock frequencies: 125 MHz, 100 MHz, and 83 MHz.
Key features include programmable CAS latency (2 or 3), programmable burst length (1, 2, 4, or 8), sequential or interleaved burst types, auto‑precharge, and both auto‑refresh and self‑refresh modes. The device is supplied in a 400‑mil, 54‑pin TSOP (II) package and provides separate power pins for core (Vdd/Vss) and output buffers (VddQ/VssQ).
| Clock frequency | 125 MHz / 100 MHz / 83 MHz |
|---|---|
| CAS latency | 2 or 3 (programmable) |
| Burst length | 1, 2, 4, 8 (programmable) |
| Package type | 400‑mil, 54‑pin Thin Small Outline Package (TSOP‑II) |
| Memory density | 64 Mbit |
| Interface | LVTTL (also SSTL option) |
| Power supply | Single 3.3 V + 0.3 V (Vss) |
The device can operate up to 125 MHz.
CAS latency can be set to 2 or 3 cycles and is programmable.
It is supplied in a 400‑mil, 54‑pin Thin Small Outline Package (TSOP‑II).
The chip provides a total density of 64 Mbit.