The A43P26161 is a low power synchronous DRAM with a capacity of 1M X 16 bits X 4 banks. It features low power supply, LVCMOS compatibility, four banks, and MRS cycle programming.
The A43P26161 is a 67,108,864‑bit low‑power synchronous DRAM organized as 4 banks of 1,048,576 words by 16 bits. It is offered in 54‑ball CSP (8 mm × 8 mm) and 54‑pin TSOP(II) packages and operates from –40 °C to +85 °C.
Key features include low‑power supply (VDD 2.3‑2.7 V), selectable CAS latency of 2 or 3, burst lengths of 1, 2, 4, 8 or full page, and a maximum clock frequency of 133 MHz (105 MHz at CL = 3). The datasheet details pin assignments, absolute maximum ratings, DC and AC electrical characteristics, and recommended decoupling capacitance.
| Capacity | 67,108,864 bits |
|---|---|
| Organization | 4 banks × 1,048,576 words × 16 bits |
| Supply Voltage (VDD) | 2.3‑2.7 V |
| Supply Voltage (VDDQ) | 2.3‑2.7 V |
| CAS Latency | 2 and 3 |
| Burst Length | 1, 2, 4, 8, full page |
| Operating Temperature | -40 °C to +85 °C |
| Package Types | 54‑ball CSP (8 mm × 8 mm) and 54‑pin TSOP(II) |
| Input Capacitance | 2.0‑4.0 pF |
It is offered in a 54‑ball CSP (8 mm × 8 mm) and a 54‑pin TSOP(II) package.
The DRAM operates from –40 °C up to +85 °C.