The document provides information about the ADAU1761, a SigmaDSP stereo audio codec with low power consumption, 96 kHz sampling rate, and 24-bit resolution. The codec includes an integrated PLL for clock generation, supporting input clocks from 8 MHz to 27 MHz. It features a fully programmable 28-/56-bit digital audio processor, 24-bit stereo audio ADC and DAC, low power record and playback modes, and flexible analog input/output mixers.
The ADAU1761 is a low‑power, 24‑bit stereo audio codec with an integrated SigmaDSP core. It offers programmable analog and digital signal paths, flexible input mixers, a stereo digital microphone input, and multiple analog output drivers for headphones, earpieces, or line‑level connections. The device supports sampling rates from 8 kHz to 96 kHz and includes on‑chip PLL, automatic level control, and click‑less mute functions.
The handbook provides full specifications, pin configurations, power‑management details, and typical current consumption figures. It also includes application notes for smartphones, digital cameras, portable media players, and other multimedia devices, along with ordering information for the ADAU1761 package options.
| ADC Resolution | 24 bits |
|---|---|
| DAC Resolution | 24 bits |
| Typical Record Current (AVDD = 3.3 V, 48 kHz) | 5.24 mA |
The codec provides six analog input pins that can be configured for single‑ended or differential operation.
Typical current consumption is about 5.24 mA for recording stereo differential to the ADC.