This manual introduces the features and applications of the dsPIC33FJXXXGPX06/X08/X10 high performance 16-bit digital signal controllers
This handbook describes the high‑performance 16‑bit dsPIC33FJXXXGPX series, covering its Harvard‑architecture CPU core, DMA engine, interrupt controller, digital I/O, flash and SRAM capacities, and system management features such as clock options and power‑saving modes. It also lists the supported peripherals including ADC, UART, CAN, and timer/PWM modules.
Detailed pin‑out diagrams for 64‑, 80‑ and 100‑pin TQFP packages are included, along with a family table that shows device variants, memory sizes, and available peripherals. Ordering information, product identification codes, and global sales contacts are provided at the end of the document. This manual is written in Chinese.
| Maximum MIPS | 40 MIPS |
|---|---|
| Operating Temperature Range | -40°C to +85°C |
| Flash Program Memory | 256 KB |
| SRAM | 30 KB (including 2 KB DMA RAM) |
| Maximum Digital I/O Pins | 85 pins |
| DMA Channels | 8 channels |
The device can achieve up to 40 MIPS at 3.0‑3.6 V supply.
Up to 85 digital I/O pins can be programmed.
It operates from –40 °C to +85 °C, suitable for industrial environments.
The controller includes up to 256 KB of flash program memory.