The ADF4193 is a low phase noise, fast settling PLL frequency synthesizer. It features a new, fast settling, fractional-N PLL architecture that replaces ping-pong synthesizers. Its key features include: frequency hopping across the GSM band in 5 µs with phase settled within 20 µs; 0.5° rms phase error at 2 GHz RF output; digitally programmable output phase; RF input range up to 3.5 GHz; 3-wire serial interface; on-chip, low noise differential amplifier; phase noise figure of merit: −216 dBc/Hz; qualified for automotive applications. Applications include GSM/EDGE base stations, PHS base stations, instrumentation and test equipment.
The ADF4193 frequency synthesizer provides a single‑PLL solution for GSM/EDGE base‑station local oscillators. It features a fractional‑N architecture, 3‑wire serial interface, on‑chip differential amplifier, and low‑noise performance suitable for high‑speed wireless applications. The device is qualified for automotive environments and supports RF input up to 3.5 GHz.
Key specifications include an RF input range of 0.4‑3.5 GHz, normalized phase noise of –216 dBc/Hz, and a maximum serial clock rate of 33 MHz. The part is offered in a 32‑lead chip‑scale package (LFCSP) with detailed PCB layout guidelines and an extensive register map for flexible configuration.
| Operating Temperature Range (Automotive) | –40 °C to +105 °C |
|---|---|
| Maximum Serial Clock Rate | 33 MHz |
The serial clock can run up to 33 MHz.