This document is the dsPIC30F6010 datasheet from Microchip Technology Inc. in 2004, which describes the features and characteristics of the high-performance digital signal controller.
The dsPIC30F6010 is a 16‑bit digital signal controller from Microchip that combines a modified Harvard‑architecture CPU with extensive DSP capabilities. It offers up to 30 MIPS performance, a 144 KB Flash program memory, 8 KB RAM, and a range of peripheral modules for motor control, communication, and analog conversion.
The datasheet details the device’s architecture, memory organization, interrupt system, and peripheral features such as UART, CAN, SPI, I²C, PWM, and a 10‑bit ADC capable of 500 Ksps conversion. It also provides electrical characteristics, packaging information, and ordering details.
| Flash program memory | 144 KB |
|---|---|
| Data RAM | 8 KB |
| Data EEPROM | 4 KB |
| Maximum performance | 30 MIPS |
| External clock input range | DC to 40 MHz |
| Interrupt sources | 44 total (5 external) |
| UART modules | 2 with FIFO buffers |
| CAN modules | 2 (2.0B compliant) |
| ADC resolution | 10‑bit |
| ADC conversion rate | 500 Ksps |
| I/O pin drive capability | 25 mA sink / 25 mA source |
The device provides 144 KB of on‑chip Flash program memory.
It includes two UART modules, each with FIFO buffers.
The controller can operate at up to 30 MIPS.