The ISL6210 is a dual-power synchronous rectified MOSFET driver from Intersil. It is optimized to drive two independent power channels in a synchronous-rectified buck converter topology. The ISL6210 together with an Intersil ISL62xx multiphase PWM controller forms a complete single-stage core-voltage regulator solution with high efficiency performance at high switching frequency for advanced microprocessors. The IC is biased by a single low voltage supply (5V), minimizing driver switching losses in high MOSFET gate capacitance and high switching frequency applications. Each driver is capable of driving a 3nF load with less than 10ns rise/fall time. Bootstrapping of the upper gate driver is implemented via an internal low forward drop diode, reducing implementation cost, complexity, and allowing the use of higher performance, cost effective N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. The ISL6210 features 4A typical sink current for the lower gate driver, enhancing the lower MOSFET gate hold-down capability during PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6210 also features an input that recognizes a high- impedance state, working together with Intersil multiphase PWM controllers to prevent negative transients on the controlled output voltage when operation.
The ISL6210 integrates two dual‑channel MOSFET drivers optimized for synchronous‑rectified buck converters. It operates from a single 5 V supply and offers adaptive shoot‑through protection, low on‑resistance and up to 4 A sink current per channel.
The document details absolute maximum ratings, electrical specifications, pin functions, timing diagrams, recommended PCB layout, thermal management and package dimensions for the 16‑lead QFN and MLFP variants.
| Ambient temperature operating range | -40 °C to +125 °C |
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The driver monitors the lower gate voltage and only enables the upper gate after the lower gate falls below 1 V, preventing simultaneous conduction.