The TS80C31X2 is a high performance CMOS and ROMless version of the 80C51 CMOS single chip 8-bit microcontroller. It retains all the features of the TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscillator and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C31X2 has 2 software-selectable modes: idle mode, power-down mode and power-off flag, once mode (on-chip emulation).
The TS80C31X2 is a high‑performance CMOS, ROM‑less 8‑bit microcontroller compatible with the 80C31 core. It retains the classic 5‑source, 4‑priority interrupt system, dual data pointer, enhanced UART and adds X2 speed improvement, power‑down and idle modes, and a power‑off flag. The device operates from 4.5‑5.5 V (or 2.7‑5.5 V) and offers commercial (0 °C‑70 °C) and industrial (‑40 °C‑85 °C) temperature ranges.
The document details the block diagram, special‑function‑register (SFR) mapping, pin assignments for PDIL40, PLCC44 and VQFP44 packages, and the CKCON register that controls the X2 feature. It also lists the electrical specifications, maximum operating frequency (up to 60 MHz), and package options.
| Internal RAM | 128 bytes |
|---|---|
| I/O Ports | Four 8‑bit ports |
| Temperature Range | Commercial 0‑70 °C, Industrial ‑40‑85 °C |
| Package | PDIL40, PLCC44, VQFP44 |
| Memory Type | ROM‑less |
The X2 option reduces the core cycle to 6 clock periods per machine cycle, allowing either double CPU speed or halving the crystal frequency.
The device provides four 8‑bit I/O ports.
It supports idle mode, power‑down mode, and a power‑off flag, plus an ONCE mode for reduced activity.
The microcontroller includes 128 bytes of scratchpad RAM.