Analog Devices AD8159 Datasheet

The AD8159 Rev. A is a 3.2 Gbps quad buffer multiplexer/demultiplexer with port-level 2:1 mux/1:2 demux functionality. Each port consists of 4 lanes, with each lane running from dc to 3.2 Gbps independently. It compensates for over 40 inches of FR4 at 3.2 Gbps through two levels of input equalization or four levels of output pre-emphasis. The product accepts ac- or dc-coupled differential CML inputs and has low deterministic jitter, low random jitter, and a BER of less than 10^-16. It also features on-chip termination, reversible inputs and outputs on one port, unicast or bicast on the 1:2 demux function, port-level loopback capability, and single lane switching capability. The AD8159 operates on a 3.3 V core supply and has a flexible I/O supply down to 2.5 V. It is a low power device, typically consuming 1 W in the basic configuration. The operating temperature range is -40°C to +85°C. The AD8159 is suitable for applications such as low-cost redundancy switches and SONET OC48/SDH16 and lower data rates.


Analog Devices AD8159 Datasheet - cover page
Brand
ANNLOG
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
24
File format
PDF
File size
580 KB
Published
26 March, 2012
Updated
28 September, 2023
MD5 checksum
59E0ABA874B691AA2E0D64C8342026FB

About this manual

The AD8159 is an asynchronous, protocol‑agnostic quad‑lane 2:1 switch with 12 differential inputs and 12 differential outputs. Each lane operates independently up to 3.2 Gbps and offers two levels of input equalization and four levels of output pre‑emphasis, providing low deterministic jitter (20 ps p‑p) and low random jitter (1 ps rms).

Typical applications include low‑cost redundancy switching for backplane links such as SONET OC48/SDH16, XAUI, Gigabit Ethernet, Fibre Channel, Infiniband, and PCI‑Express. The device also supports unicast/bicast operation, reversible ports, and loopback for testing high‑speed serial links.

What's inside

  • Features
  • Applications
  • General Description
  • Functional Block Diagram
  • Specifications
  • Absolute Maximum Ratings
  • ESD Caution
  • Pin Configuration and Function Descriptions
  • Typical Performance Characteristics

Specifications

Data Rate/Channel (NRZ)3.2 Gbps
Propagation Delay (input to output)600 ps
Lane‑to‑Lane Skew100 ps
Switching Time5 ns
Output Rise/Fall Time (20%‑80%)100 ps
Input Bias Current4 pA
Core Supply Voltage (VEE)3.0‑3.6 V
Operating Temperature Range-40 °C to +85 °C

Frequently asked questions

What is the maximum data rate per lane?

Each lane supports up to 3.2 Gbps.

What supply voltage range is required for the core?

The core supply voltage must be between 3.0 V and 3.6 V.

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