DDR memory is a new memory technology that not only increases memory bandwidth but also reduces memory power consumption. DDR memory uses SSTL_2 logic and operates at a lower voltage, making it suitable for mobile applications.
The document introduces the ISL6225 dual PWM controller, which combines two synchronous PWM regulators to provide the required 2.5 V VDDQ and 1.25 V V77 rails for DDR memory systems. It explains the need for precise VREF and VTT termination voltages and shows how the IC can both source and sink current on one channel.
A quick‑start evaluation board (ISL6225EVAL1) is described, with jumper settings, power connections, and a bill of materials. Measured performance data such as efficiency, transient response, and typical current consumption are presented, along with schematics and layout diagrams.
| VDDQ output voltage | 2.5 VDC |
|---|---|
| V77 output voltage | 1.25 VDC |
| VTT termination voltage tolerance | ±40 mV of VREF |
| Maximum VTT supply current | 2.025 A |
| Typical VTT line current | 16.2 mA per line |
| Base VDDQ current range | 2.0–3.0 A |
| Peak VDDQ current | up to 4.0 A |
Each terminated line consumes 16.2 mA of current.
The VTT supply can deliver up to 2.025 A of current.
The VDDQ rail has a permanent base current in the range of 2.0 A to 3.0 A.